SPI1 DDR control register
| SPI_FMEM_DDR_EN | 1: in DDR mode, 0: in SDR mode. |
| SPI_FMEM_VAR_DUMMY | Set the bit to enable variable dummy cycle in DDRmode. |
| SPI_FMEM_DDR_RDAT_SWP | Set the bit to reorder RX data of the word in DDR mode. |
| SPI_FMEM_DDR_WDAT_SWP | Set the bit to reorder TX data of the word in DDR mode. |
| SPI_FMEM_DDR_CMD_DIS | the bit is used to disable dual edge in command phase when DDR mode. |
| SPI_FMEM_OUTMINBYTELEN | It is the minimum output data length in the panda device. |
| SPI_FMEM_USR_DDR_DQS_THD | The delay number of data strobe which from memory based on SPI_CLK. |
| SPI_FMEM_DDR_DQS_LOOP | 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module |
| SPI_FMEM_DDR_DQS_LOOP_MODE | When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. |
| SPI_FMEM_CLK_DIFF_EN | Set this bit to enable the differential SPI_CLK#. |
| SPI_FMEM_HYPERBUS_MODE | Set this bit to enable the SPI HyperBus mode. |
| SPI_FMEM_DQS_CA_IN | Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. |
| SPI_FMEM_HYPERBUS_DUMMY_2X | Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. |
| SPI_FMEM_CLK_DIFF_INV | Set this bit to invert SPI_DIFF when accesses to flash. . |
| SPI_FMEM_OCTA_RAM_ADDR | Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}. |
| SPI_FMEM_HYPERBUS_CA | Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}. |